library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity ADDR1MUX_logic is
    port(ADDR1MUX: in bit;
         PCval,SR2: in unsigned(15 downto 0);
         ADDR1MUX_out: out unsigned(15 downto 0));
     end entity ADDR1MUX_logic;
     
architecture build of ADDR1MUX_logic is
    begin
        process(ADDR1MUX,PCval,SR2)
            begin
                if ADDR1MUX = '0' then
                    ADDR1MUX_out <= PCval;
                elsif ADDR1MUX = '1' then
                    ADDR1MUX_out <= SR2;
                end if;
            end process;
    end build;
